View HSP43881GM-25883_1251409.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HSP43881/883
TM
Data Sheet
May 1999
FN2449.4
Digital Filter
The HSP43881/883 is a video speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 8 x 8-bit multiplier, three decimation registers and a 26-bit accumulator. The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8-bits. The HSP43881/883 has a maximum sample rate of 25.6MHz. The effective multiply accumulate (mac) rate is 204MHz. The HSP43881/883 DF can be configured to process expanded coefficient and word sizes. Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process larger filter lengths at less than 25.6MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The DF provides for 8-bit unsigned or two's complement arithmetic, independently selectable for coefficients and signal data. Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/2, 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as matrix multiplication and N x N spatial correlations/convolutions for image processing applications.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 0MHz to 25.6MHz Sample Rate * Eight Filter Cells * 8-Bit Coefficients and Signal Data * Low Power CMOS Operation * ICCSB 500A Maximum * ICCOP 160mA Maximum at 20MHz * 26-Bit Accumulator Per Stage * Filter Lengths Up to 1032 Taps * Expandable Coefficient Size, Data Size and Filter Length * Decimation by 2, 3 or 4
Applications
* 1-D and 2-D FIR Filters * Radar/Sonar * Adaptive Filters * Echo Cancellation * Complex Multiply-Add * Sample Rate Converters
Ordering Information
PART NUMBER HSP43881GM-25/883 TEMP. RANGE (oC) -55 to 125 PACKAGE 85 Ld PGA PKG. NO. G85.A
Block Diagram
VCC DIENB CIENB DCMO - 1 ERASE TCCI CIN0 - 7 RESET CLK ADR0 - 2 RESET CLK SHADD SENBL SENBH 8 5 VSS DIN0 - DIN7 TCS 8 5 8 DF FILTER CELL 0 5 3 MUX ADR0, ADR1, ADR2 2 26 OUTPUT STAGE 2 SUM0 - 25 26 26 8 8 DF FILTER CELL 1 26 8 8 DF FILTER CELL 2 26 8 8 DF FILTER CELL 3 26 8 8 DF FILTER CELL 4 26 8 8 DF FILTER CELL 5 26 8 8 DF FILTER CELL 6 26 8 8 DF FILTER CELL 7 26 TCCO 8 COUT0 - 7 COENB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HSP43881/883 Pinouts
85 PIN PGA TOP VIEW, PINS DOWN
1 A B VSS VCC
2 COENB COUT7
3 VCC TCCO ALIGN PIN
4 RESET ERASE
5 DIN7 TCS
6 DIN6 DIN1
7 DIN3 DIN2
8 DIN0 CIENB
9 TCCI CIN7
10 VCC CIN6
11 VSS CIN4
C
COUT5 COUT6
DIENB
DIN5
DIN4
CIN5
CIN3 VCC SENBL
D
COUT3 COUT4
CIN2
E
COUT1
VSS
COUT2
CIN1
CIN0
F G
VSS ADR2
COUT0 SHADD DCM0 CLK
SUM0 SUM1
VCC SUM3
VSS SUM2
H J
ADR1 VCC
ADR0 SUM25 SUM20 SUM17 SUM16
SUM5 SUM7
SUM4 VSS SUM6
K
SENBH SUM24
VSS SUM22
VCC SUM21
SUM19
VSS SUM14
SUM15
SUM12
SUM10
SUM8
L
DCM1
SUM23
SUM18
VCC
SUM13
VSS
SUM11
SUM9
2
HSP43881/883 Pinouts
(Continued) 85 PIN PGA BOTTOM VIEW, PINS UP
1 2 3 4 5 6 7 8 9 10 11
L DCM1 K SENBH J VCC H ADR1 G ADR2 F VSS E COUT1 D COUT3 C COUT5 COUT6 B VCC A VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS COUT7 COUT8 ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 ALIGN PIN DIENB DIN5 DIN4 CIN5 CIN3 COUT4 CIN2 VCC VSS COUT2 CIN1 CIN0 SENBL COUT0 SHADD SUM0 VCC VSS DCM0 CLK SUM1 SUM3 SUM2 ADR0 SUM5 SUM4 SUM25 SUM20 SUM17 SUM16 SUM7 VSS SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9
NOTE: An overbar on a signal name represents an active LOW signal.
3
HSP43881/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Input, Output Voltage . . . . . . . . . . . . . . . . . . GND -0.5 to VCC +0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PGA Package. . . . . . . . . . . . . . . . . . . . 36.0 7.0 Maximum Package Power Dissipation at 125oC PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44W Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperate Range . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,762 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage SYMBOL VIH VIL VOH VOL II IO VIHC VILC ICCSB TEST CONDITIONS VCC = 5.5V VCC = 4.5V IOH = -400A VCC = 4.5V (Note 2) IOH = -400mA VCC = 4.5V (Note 2) VIN = VCC or GND VCC = 4.5V VIN = VCC or GND VCC = 5.5V VCC = 5.5V VCC = 4.5V VIN = VCC or GND VCC = 5.5V, Outputs Open f = 20.0MHz VCC = 5.5V (Note 3) (Note 4) GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 MAX UNITS V
1, 2, 3
-
0.8
V
1, 2, 3
2.6
-
V
Output LOW Voltage
1, 2, 3
-
0.4
V A A
Input Leakage Current
1, 2, 3
-10
+10
Output Leakage Current
1, 2, 3
-10
+10
Clock Input High Clock Input Low Standby Power Supply Current
1, 2, 3 1, 2, 3 1, 2, 3
3.0 -
0.8 500
V V A
Operating Power Supply Supply Current Functional Test NOTES:
ICCOP FT
1, 2, 3
-55 TA 125 -55 TA 125
-
160.0
mA
7, 8
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8.0mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH 1.5V, VOL 1.5V, VIHC = 3.4V and VILC = 0.4V.
4
HSP43881/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUP S 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -25 (25.6MHz) TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 39 16 16 17 0 MAX 20 15 25 UNITS ns ns ns ns ns ns ns ns
PARAMETER Clock Period Clock Low Clock High Input Setup Input Hold CLK to Coefficient Output Delay Output Enable Delay CLK TO SUM Output Delay NOTE:
SYMBOL t CP tCL tCH tIS tIH tODC tOED tODS
NOTES Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5
5. AC Testing: VCC - 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0". Input and output timing measurements are made at 1.5V for both a Logic "1" an"). CLK is driven at 4.0V and 0V and measured at 2.0V.
TABLE 3. AC ELECTRICAL PERFORMANCE SPECIFICATIONS TEST CONDITIONS VCC = Open, f = 1MHz All measurements are referenced to device GND TEMP (oC) TA = 25 -25 (25.6MHz) MIN MAX 15 UNITS pF
PARAMETER Input Capacitance
SYMBOL CIN
NOTES 6
Output Capacitance Output Disable Delay Output Rise Time Output Fall Time NOTES:
COUT t ODD t OR t OF
6 6, 7 6, 7 6, 7
TA = 25 -55 TA 125 -55 TA 125 -55 TA 125
-
15 15 6 6
pF ns ns ns
6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 7. Loading is as specified in the test load circuit, CL = 40pF.
TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
5
HSP43881/883 Burn-In Circuit
BOTTOM VIEW, PINS UP
1 L DCM1 K SENBH J VCC H ADR1 G ADR2 F VSS E COUT1 D COUT3 C COUT5 COUT6 B VCC A VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 TCCI VCC VSS COUT7 TCCO ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 ALIGN PIN DIENB DIN5 DIN4 CIN5 CIN3 COUT4 CIN2 VCC VSS COUT2 CIN1 CIN0 SENBL COUT0 SHADD SUM0 VCC VSS DCM0 CLK SUM1 SUM3 SUM2 ADR0 SUM5 SUM4 SUM25 SUM20 SUM17 SUM16 SUM7 VSS SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 2 3 4 5 6 7 8 9 10 11
6
HSP43881/883
BURN-IN SIGNALS PGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 NOTES: 8. VCC/2 (2.7 10% used for outputs only. 9. 47k (20%) resistor connected to all pins except VCC and GND. 10. VCC = 5.5V 0.5V. 11. 0.1F (minimum) capacitor between VCC and GND per device. 12. F0 = 100kHz 10%, F1 = F0/2, F2 = F1/2..., F11 = F10/2, 40% - 60% duty cycle. 13. Input voltage limits: VIL = 0.8V maximum, VIH = 4.5V 10%. VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 CIN8/5CCI VCC VSS VCC COUT7 COUT8/TCC0 ERASE DIN8/TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 PIN NAME BURN-IN SIGNAL GND F10 VCC F11 F8 F6 F3 F0 F8 VCC GND VCC VCC/2 VCC/2 F10 F7 F1 F2 F10 F7 F6 F4 PGA PIN C1 C2 C3 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3 F9 PIN NAME COUT5 COUT6 ALIGN DIENB DIN5 DIN4 CIN5 CIN3 COUT3 COUT4 CIN2 VCC COUT1 VSS COUT2 CIN1 CIN0 SENBL VSS COUT0 SHADD SUM0 BURN-IN SIGNAL VCC/2 VCC/2 NC F10 F5 F4 F5 F3 VCC/2 VCC/2 F2 VCC VCC/2 GND VCC/2 F1 F0 F10 GND VCC/2 F9 VCC/2 PGA PIN F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1 K2 K3 PIN NAME VCC VSS ADR2 DCMO CLK SUM1 SUM3 SUM2 ADR1 ADR0 SUM5 SUM4 VCC SUM25 SUM20 SUM17 SUM16 SUM7 VSS SENBH SUM24 VSS BURN-IN SIGNAL VCC GND F2 F5 F0 VCC/2 VCC/2 VCC/2 F1 F0 VCC/2 VCC/2 VCC VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 GND F10 VCC/2 GND PGA PIN K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 PIN NAME VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 BURN-IN SIGNAL VCC VCC/2 GND VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 F6 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC VCC/2 GND VCC/2 VCC/2
Die Characteristics
DIE DIMENSIONS: 328 mils x 283 mils x 1 mil METALLIZATION: Type: Si-Al or Si-AI-Cu Thickness: 8kA GLASSIVATION Type: Nitrox Silox Thickness: 10kA WORST CASE CURRENT DENSITY: 1.2 x 105 A/cm2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7

▲Up To Search▲

Price & Availability of HSP43881GM-25883

	To Download HSP43881GM-25883 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .